In an analog integrated circuit, a reference voltage circuit (constant-voltage generating circuit) called a bandgap circuit has widely been used when it is required to provide a constant reference voltage that does not depend on temperature or supply voltage. Since it can be easily combined with a digital circuit, the bandgap circuit has also been used widely as a stable reference voltage circuit in many important CMOS analog integrated circuits.
In the prior art, various kinds of circuits that obtain a temperature-independent reference voltage by adding a forward biased pn junction voltage to a voltage proportional to absolute temperature (T) (generally described as PTAT—Proportional To Absolute Temperature) have been devised and commercially implemented as bandgap circuits.
It is known that the forward biased pn junction voltage, if approximated by a linear equation, or in the range where it can be approximated by a linear equation, is negatively linearly dependent on absolute temperature (generally described as CTAT (Complementary To Absolute Temperature)). It is also known that by adding a (suitable) PTAT voltage to this forward biased pn junction voltage, a reference voltage substantially independent of temperature can be obtained.
Of such prior art bandgap circuits, the most standard one is illustrated in FIG. 1.
In FIG. 1, Q1 and Q2 are pnp bipolar transistors (hereinafter abbreviated pnp BJTs), R1, R2, and R3 are resistors (their values are also designated by R1, R2, and R3), AMP1 is an operational amplifier circuit, GND is a GND terminal, Vbgr is an output (reference voltage), and NODE1, IM, and IP are internal nodes. The values illustrated alongside the resistors are examples of the resistance values, and the number affixed to each BJT indicates the relative area ratio of the BJT.
The operation of the prior art circuit of FIG. 1 will be explained briefly.
It is known that, denoting the base-emitter voltage of a BJT or the forward bias voltage of a pn junction by Vbe, the relationship between the forward bias voltage of the pn junction and the absolute temperature T is roughly given by the following equation (1).Vbe=Veg−aT  (1)where Vbe is the forward bias voltage of the pn junction, Veg is the silicon bandgap voltage (about 1.2 V), “a” is the temperature dependence of Vbe (about 2 mV/° C.), and T is the absolute temperature. The value of “a” varies depending on the bias current, but it is known to be about 2 mV/° C. in the operating range.
It is also known that the relationship between the emitter current IE of the BJT and the voltage Vbe is roughly given by the following equation (2).IE=IOexp(qVbe/kT)  (2)where IE is the emitter current of the BJT or diode current, IO is a constant (proportional to area), q is the electron charge, and k is the Boltzmann constant.
By the negative feedback action of the operational amplifier AMP1, when the voltage gain of AMP1 is sufficiently large, the potentials at the inputs IM and IP to the AMP1 become (substantially) equal and the circuit stabilizes. In this case, if the resistance ratio of R1 to R2 is, for example, chosen to be 1:10 (100 k:1M) as illustrated in FIG. 1, then the ratio of the magnitude of the current flowing through Q1 to that through Q2 is 10:1, hence the current flowing through Q1 is designated by 10I and that through Q2 by I. I×10 and I illustrated below Q1 and Q2 indicate the relationship between these currents.
If the emitter area of Q2 is 10 times the emitter area of Q1 (×1 and ×10 affixed to Q1 and Q2 in FIG. 1 indicate the relationship between these emitter areas), then denoting the base-emitter voltage of Q1 by Vbe1 and the base-emitter voltage of Q2 by Vbe2, the relations expressed the following equations (3) and (4) are obtained from the equation (2).10×I=IOexp(qVbe1/kT)  (3)I=10×IOexp(qVbe2/kT)  (4)
Eliminating I from the equations (3) and (4), the following equation (5) is obtained.10O=exp(qVbe1/kT−qVbe2/kT)  (5)
Here, setting Vbe1−Vbe2=ΔVbe, the following equation (6) is obtained.ΔVbe=(kT/q)ln(100)  (6)
As shown by the equation (6), the difference ΔVbe between the base-emitter voltages of Q1 and Q2 is expressed by the logarithm (ln(100)) of the Q1/Q2 current density ratio 100 and the thermal voltage (kT/q). In FIG. 1, IP is at Vbe1, NODE1 is at Vbe2, and IM and IP are equal; therefore, this ΔVbe represents the potential difference across the resistor R3, and the current of ΔVbe/R3 flows through the resistors R2 and R3.
Hence, the potential difference VR2 across the resistor R2 is expressed by the following equation (7).VR2=ΔVbeR2/R3  (7)
Since the potential IM becomes equal to the potential IP, i.e., Vbe1, as described above, the potential of the reference voltage Vbgr is expressed by the following equation (8).Vbgr=Vbe1+ΔVbeR2/R3  (8)
As shown by the equation (1), the forward bias voltage Vbe1 of the pn junction has a negative temperature dependence and decreases with increasing temperature. On the other hand, ΔVbe increases with increasing temperature as shown by the equation (6). Accordingly, by suitably selecting the constant so as to cancel the change of Vbe1 by ΔVbeR2/R3, the circuit can be designed so that the value of the reference voltage Vbgr does not depend on temperature. The value of BGROUT in that case is about 1.2 V (1200 mV), which corresponds to the silicon bandgap voltage.
In this way, by suitably selecting the circuit constant in the prior art circuit of FIG. 1, the temperature independent bandgap voltage can be generated using relatively simple circuitry.
While the prior art circuit of FIG. 1 has the advantage that the reference voltage can be generated using relatively simple circuitry as described above, it also has a shortcoming as will be described below.
FIG. 2 is a diagram for explaining the problem associated with the prior art circuit of FIG. 1. In the diagrams given hereinafter, corresponding parts are designated by the same reference characters, unless specifically stated otherwise.
In FIG. 2, IAMP1 is an ideal operational amplifier circuit, VOFF is an equivalent voltage source which represents the offset voltage of the operational amplifier, and IIM is a negative input terminal of the ideal operational amplifier IAMP1.
In FIG. 2, in order to explain the problem associated with the prior art circuit of FIG. 1, AMP1 in FIG. 1 is represented by the ideal operational amplifier IAMP1 and the equivalent offset voltage VOFF. The basic operation of the circuit of FIG. 2 is the same as that described with reference to FIG. 1, and the following describes how the offset voltage VOFF affects the output voltage Vbgr.
When forming a bandgap circuit using a CMOS circuit, especially a bandgap circuit such as illustrated in FIG. 1, the effect of the offset voltage associated with the operational amplifier is unavoidable. Ideally, when the input potentials IM and IP to AMP1 of FIG. 1 are equal, the output potential of AMP1 will become equal to (for example) about one half of the supply voltage. However, in a practical integrated circuit, the characteristics of the devices forming each amplifier are not perfectly identical. As a result, the input potentials with which the output potential of AMP1 becomes equal to (for example) about one half of the supply voltage differ for each individual amplifier, and the difference that develops between the input potentials at this time is called the offset voltage. It is known that a typical offset voltage is about ±10 mV.
To explain how the characteristics of the practical amplifier affect the output voltage of the bandgap circuit, AMP1 in FIG. 1 is represented in FIG. 2 by a combination of the ideal operational amplifier IAMP1 and the equivalent offset voltage VOFF. Here, the offset voltage of the ideal operational amplifier IAMP1 is 0 mV.
In the ideal circuit of FIG. 1, the potentials IM and IP are identical. On the other hand, in the practical circuit, since the input potentials IIM and IP to the virtual ideal operational amplifier are identical, the potentials IM and IP differ by an amount equal to the offset voltage VOFF. For simplicity, the potential difference that would develop under an ideal condition across the resistor R3 is expressed by the following equation (9).VR3=ΔVbe  (9)
The potential difference VR3′ that develops across the resistor R3 in FIG. 2 is expressed by the following rough equation (9′).VR3′=ΔVbe+VOFF  (9′)
It is to be understood here that VOFF indicates the value of the offset voltage VOFF.
The potential difference VR2′ across the resistor R2 is expressed by the following equation (10).VR2′=(ΔVbe+VOFF)R2/R3  (10)
Hence, Vbgr is expressed by the following equation (11).Vbgr=Vbe1+VOFF+(ΔVbe+VOFF)R2/R3  (11)
If it is assumed that R2/R3=5 as illustrated in FIG. 2, the value of Vbgr is equal to the sum of the ideal value and the offset value multiplied by (about) 6.
In the circuit examples illustrated in FIGS. 1 and 2, in order to minimize the effect of the offset voltage of the operational amplifier, the area of Q2 is set to be 10 times that of Q1 and the current flowing through Q1 is set to be 10 times the current flowing through Q2. Accordingly, the potential difference across R3, for example, is given by the following equation (12).ΔVbe=(kT/q)ln(100)=26 mV×4.6=120 mV  (12)
As shown by the equation (12), the potential difference can be made relatively large at 120 mV. The effect of VOFF can be held relatively low in this way but, even in this case, if the bandgap voltage of 1200 mV is to be obtained by adding the PTAT voltage to the Vbe of about 600 mV, the value of the equation (12) must be multiplied by 5 and added to Vbe1. As a result, if the offset voltage VOFF is present, the effect of VOFF on Vbgr is multiplied by about (1+5)=6. (The Vbgr equation illustrated in FIG. 2 indicates this effect of the offset voltage.)
Specifically, while the circuit of FIG. 1 has the advantage that the bandgap circuit can be constructed with relatively simple circuitry, it has the limitation that the accuracy of the reference voltage Vbgr that can be achieved is limited by the offset voltage of the operational amplifier circuit.
To solve the above problem, there is proposed a so-called chopper-stabilized bandgap circuit (chopper-stabilized BGR) that switches its internal operation so as to alternately produce outputs for canceling the offset.
FIG. 3A is a diagram illustrating circuit configuration of a prior art chopper-stabilized bandgap circuit and FIG. 3B is a diagram illustrating switch signals and changes in output that occur in the circuit of FIG. 3A. The principle of operation of the prior art chopper-stabilized bandgap circuit will be described with reference to FIGS. 3A and 3B.
In FIGS. 3A and 3B, SW1, SW2, SW3, and SW4 are switches, IAMP2 is an ideal operational amplifier circuit, NODE2 and NODE3 are internal nodes, 10 is a switch signal generating circuit which generates switch signals φ1 and φ2, and 11 is an LPF (low-pass filter). The signal names φ1 and φ2 illustrated alongside the switches SW1 to SW4 indicate the periods during which the respective switches are closed; i.e. SW2 and SW3 are closed during the H (high) period of φ1 (hereinafter called the φ1 period), and SW1 and SW4 are closed during the H (high) period of φ2 (hereinafter called the φ2 period). The timing of the signals φ1 and φ2 is illustrated in FIG. 3B. The switch signal generating circuit can generate the switch signals φ1 and φ2 from a clock or can use the clock and its inverted version as the switch signals φ1 and φ2.
The operation of the prior art circuit of FIGS. 3A and 3B will be briefly described.
During the H (high) period of φ1 (the φ1 period), the circuit of FIG. 3A operates in a manner similar to the circuit of FIGS. 1 and 2. As described with reference to FIGS. 1 and 2, the offset voltage VOFF (for example) is multiplied by 6 and added to the ideal bandgap output to produce the output BGROUT. It is assumed that the value of BGROUT at this time is, for example, equal to the ideal value (1200 mV)+6×VOFF.
In the circuit of FIG. 3A, by interchanging the connections of IM and IP relative to NODE2 and NODE3 by means of the switches SW1 to SW4, BGROUT is set equal to the ideal value (1200 mV)−6×VOFF during the φ2 period. Specifically, in the φ1 period, IM and IP are connected to NODE2 and NODE3, respectively, but in the φ2 period, the connections are interchanged so as to connect IM to NODE3 and IP to NODE2. Further, to achieve the negative feedback by IAMP2 in the φ2 period as well, the circuit is configured so that the negative input of IAMP2 functions as an inverting input during the φ1 period and as a noninverting input during the φ2 period. Likewise, the circuit is configured so that the positive input of IAMP2 functions as a noninverting input during the φ1 period and as an inverting input during the φ2 period. As a result, as illustrated in FIG. 3B, the potential on the output BGROUT changes in synchronism with φ1 and φ2 so that the output voltage becomes equal to the ideal value (1200 mV)+6×VOFF during the φ1 period and equal to the ideal value (1200 mV)−6×VOFF during the φ2 period.
The potential on BGROUT changing in synchronism with φ1 and φ2 is input to the LPF (low-pass filter) 11 to extract its DC component; in this way, a reference voltage that does not contain errors caused by the offset VOFF can be obtained. Specifically, the circuit of FIG. 3A functions as a circuit that can produce an ideal reference voltage output by first converting errors caused by the offset into AC components by φ1 and φ2 and then removing the error components by the LPF.
FIG. 4 is a diagram illustrating the amplifier circuit of FIG. 3A in further detail at the transistor level. In FIG. 4, VDD is a power supply terminal, ND1, ND2, NG1, and NG2 are internal nodes, PBIAS1 is a bias potential, PM1 to PM4 are PMOS transistors, and NM1 to NM3 are NMOS transistors. Switches SW1 to SW8 operate in the same manner as in FIGS. 3A and 3B in accordance with the signal names φ1 and φ2 placed alongside them.
SW1 to SW4 operate to connect either PM2 or PM3 to IM and the other one to IP. For example, in the φ1 period, the gate of PM2 is connected to IM. SW5 is closed, and NM1 acts as a diode-connected load, while on the other hand, ND2 is connected to the gate NG2 of NM3. In the φ2 period, the gate of PM3 is connected to IM, and SW6 is closed. ND1 is connected to the gate NG2 of NM3 by SW8; in this way, a negative feedback loop is formed in the φ2 period as well as in the φ1 period. Since the positive and negative inputs of the amplifier formed by PM2, PM3, NM1, and NM2 are reversed between the φ1 period and the φ2 period, the offset voltage is equal in value but opposite in sign between the φ1 period and the φ2 period, and on the average, the circuit operates as an amplifier free from offset.
In the prior art, errors caused by the offset voltage of the operational amplifier have been reduced by the chopper-stabilized bandgap circuit (chopper-stabilized BGR) such as illustrated in FIGS. 3 and 4.